Performance Analysis of a Reconfigurable Shared Memory Multiprocessor System for Embedded Applications

Darcy Cook¹ & Ken Ferens²¹JCA Electronics, 118 King Edward St. E., Winnipeg, MB. R3H0N8 Canada
²Electrical and Computer Engineering, Room E2-390 Engineering Information and Technology Complex, University of Manitoba, Winnipeg, MB R3T5V6 Canada
Email: Ken.Ferens@ad.umanitoba.ca

Abstract. This paper presents a method to predict performance of multiple processor cores in a reconfigurable system for embedded applications. A multiprocessor framework is developed with the capability of reconfigurable processors in a shared memory system optimized for stream-oriented data and signal processing applications. The framework features a discrete time Markov based stochastic tool, which is used to analyze memory contention in the shared memory architecture, and to predict the performance increase (speed of execution) when the number of processors is varied. Performance predictions for variations of other system parameters, such as different task allocations and the number of pipeline stages are possible as well. The results of the prediction tool were verified by experimental results of a green screen application developed and run on a Xilinx Virtex-II Pro FPGA with MicroBlaze soft processors. 

Keywords: FGPA; multiprocessor system; reconfigurable processors; scheduling and task partitioning; shared memory; soft core microprocessor.